Inventive concepts generally relates to fabrication of semiconductor devices, and more particularly, to a method for high performance standard cell design techniques in Fin field effect transistor (FET) based library using local layout effects (LLE).
A system on a chip or system on chip (SoC or SOC) is an integrated circuit (IC) integrating all components of a computer or other electronic system into a single chip. The SoC may contain digital, analog, mixed-signal, and/or radio-frequency functions—on a single chip substrate. Layout of SoC typically comprises of billions of transistors, with around to 1 million standard logic cells, where a Standard logic cell occupies 50-60% area of a typical microprocessor.
Two types of transistor technologies may be used in SoC's, namely a planar transistors and fin field effect transistors (FinFET's). A characteristic of the FinFET is that the FinFET has a conducting channel covered by a thin silicon structure, called as fin or a gate electrode. The fin may run between a source terminal and a drain terminal, and may allow multiple gates to operate on a single transistor. Advantages of FinFET type of transistors over planar type transistors may include improved speed, reduced dynamic power, reduced standby power (Leakage), reduced process variability effects, short channel effects, and/or lesser area occupancy. Though FINFET may provide the aforementioned advantages, design of FINFET may be affected by various factors, including high gate capacitance which may result in increased delay and power, a quantized nature of Fins which may provide lesser design options and sub-optimal design options, and increased layout dependent effects (LLE) which may cause increased complexity.
Some of the factors to be considered while designing FinFET's include the discrete number of fins available for design. The constrained selection of device width may limit designers to choose appropriate sizes of N-MOSFET and P-MOSFET devices to achieve desired tradeoffs in performance, power, and/or robustness, making it much more difficult to achieve optimal and result-oriented β ratios (beta, which is the ratio of P and N widths) in FinFET's. Also, designers may not change the width of the transistor and may only add or subtract fins to change the drive current as fins come in discrete increments. Because of limited fin options available with FinFET, limited variants may be available. In many cases, these variants may not be sufficient to provide flexibility to the design of the SoC. Further, most of the standard cells designed are left skewed in terms of rise/fall especially, stacked designs with two or more inputs such as NAND, NOR, AO*, OA* gates. Balance for clock cells also may get affected because there is no fin combination for NFET and PFET available leading to equal delays.
Another factor for consideration includes high input capacitance of the FinFET. The parasitic/pin capacitances of FinFET are higher compared to planar transistors which results in relatively higher dynamic power numbers, as well as lesser speed FinFET's may bring a 66 percent increase in gate capacitance per micron, as compared to 28 nm process. This may correspond to the same level of the 130-nm planar node.”
A typical physical implementation of a simple Boolean function of a FinFET based standard cell is illustrated in FIG. 1. The FinFET utilizes the desired available area and employ large device widths for PFETs and NFETs for achieving maximum performance. As shown in FIG. 1, the FinFET illustrates a layout of a typical simple Boolean function cell in a multi fin multi finger format, the total device width corresponds to the number of fins multiplied with the number of fingers. The different variants of the same logic function in the same cell area may be created by varying the number of fins of P or N device within the cell area limits constrained by the cell height and poly pitch. The cell height and poly pitch for a particular standard cell library architecture may be fixed or restrictive. As shown in FIG. 1, the FinFET structure includes twelve poly structures, which means twelve PFET devices 106 on top (e.g., in an NWELL), and twelve NFET devices 104 on bottom (e.g., in a PWELL). Both the PFET and NFET sides may be called active regions 108 of the FinFET structure, wherein the horizontal lines correspond to fins 102 and the vertical bars corresponds to polysilicon, or poly structures called as fingers 110. Layouts of different variants of the same function cell of FIG. 1 are shown in FIGS. 2 and 3 with reduced number of fins on the PFET and NFET side.
The standard cell layout may also include one or more diffusion (active (RX) breaks due to layout design rules or circuit design constraints. Such diffusion breaks are of different types, and may include a Single Diffusion Break (SDB) and a Double Diffusion Break (DDB), the names referring to the number of gate polys impacted to create the diffusion break. The sample cell design with diffusion breaks are shown in FIGS. 4, 5 and 6. FIG. 4 illustrates an example formation of DDB 408 in a typical Boolean function cell layout implemented using two poly spacing. Similarly, FIGS. 5 and 6 illustrate example formation of SDBs and DDBs 1 in other variants of a typical physical design of standard cells. FIG. 5 illustrates an example formation of a double diffusion break (SDB) 508 inside the cell boundary, formed between the NFET and PFET fins 502 and formation of single diffusion breaks 512 on the cell boundaries 514. FIG. 6 illustrates example single diffusion breaks 612 created at cell boundary 614 only. There may be other variants as well where DDB may be at boundaries as well as inside the cell or only SDB at boundaries with one more SDB breaks inside the cell or any presentation using the combination of these 2 types of diffusion breaks. In the above layouts, in order to get more performance from of a given cell with maximum device widths possible, conventionally active number of fins or fingers should be increased for which the cell area correspondingly increases. Thus, cell size constraint is a problem to the designers.
Another concern is the discrete number of fins available for the design. Accordingly, the device widths are of quantized nature. This constrained selection of device width may limit designers to choose appropriate sizes of NFET or PFET devices to achieve desired tradeoffs in performance, power, and/or robustness making it more difficult to achieve desired and feature oriented β ratios (beta, which is the ratio of P and N widths) in FinFET's.
The FinFET cells designed through this conventional approach may be left skewed in terms of output rise/fall times, especially designs, for example designs for logic gates which employ stacked transistors with two or more inputs, such as simple NAND, NOR, AO*, OA* etc. Balance for clock cells also often suffers because equal fins for NFET and PFET does not necessarily translate to equal delays. Additional design options such as varying the channel length or body biasing, are more restrictive and/or are of limited benefit due to the intrinsic characteristics of FinFET technology. Local layout effects (LLE) are considered to be more complex in FinFET based technologies.
However, there are no existing arts on optimizing cell level performance itself exploiting the LLE effects for enhancing performance of the cell.
Thus, there is a desire for a system and method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE).